# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SuperSpeed DWC3 USB SoC controller

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description:
  The common content of the node is defined in snps,dwc3.yaml.

  Phy documentation is provided in the following places.

  USB2.0 PHY
  Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml

  Type-C PHY
  Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml

select:
  properties:
    compatible:
      contains:
        enum:
          - rockchip,rk3328-dwc3
          - rockchip,rk3562-dwc3
          - rockchip,rk3568-dwc3
          - rockchip,rk3576-dwc3
          - rockchip,rk3588-dwc3
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - rockchip,rk3328-dwc3
          - rockchip,rk3562-dwc3
          - rockchip,rk3568-dwc3
          - rockchip,rk3576-dwc3
          - rockchip,rk3588-dwc3
      - const: snps,dwc3

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description:
          Controller reference clock, must to be 24 MHz
      - description:
          Controller suspend clock, must to be 24 MHz or 32 KHz
      - description:
          Master/Core clock, must to be >= 62.5 MHz for SS
          operation and >= 30MHz for HS operation
      - description:
          Controller grf clock OR UTMI clock
      - description:
          PIPE clock

  clock-names:
    minItems: 3
    items:
      - const: ref_clk
      - const: suspend_clk
      - const: bus_clk
      - enum:
          - grf_clk
          - utmi
          - pipe
      - const: pipe

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    const: usb3-otg

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

allOf:
  - $ref: snps,dwc3.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3328-dwc3
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 4
        clock-names:
          minItems: 3
          items:
            - const: ref_clk
            - const: suspend_clk
            - const: bus_clk
            - const: grf_clk
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3562-dwc3
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: ref_clk
            - const: suspend_clk
            - const: bus_clk
            - const: pipe
  - if:
      properties:
        compatible:
          contains:
            enum:
              - rockchip,rk3568-dwc3
              - rockchip,rk3576-dwc3
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          maxItems: 3
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3588-dwc3
    then:
      properties:
        clock-names:
          minItems: 3
          items:
            - const: ref_clk
            - const: suspend_clk
            - const: bus_clk
            - const: utmi
            - const: pipe

examples:
  - |
    #include <dt-bindings/clock/rk3328-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
      #address-cells = <2>;
      #size-cells = <2>;

      usbdrd3_0: usb@fe800000 {
        compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
        reg = <0x0 0xfe800000 0x0 0x100000>;
        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
                 <&cru ACLK_USB3OTG>;
        clock-names = "ref_clk", "suspend_clk",
                      "bus_clk", "grf_clk";
        dr_mode = "otg";
      };
    };
