#
core/stdarch/crates/core_arch/src/arm_shared/barrier/
cp15.rs

    1// Reference: ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360E) Section 3.5 "Summary
    2// of CP15 instructions"
    3
    4use crate::arch::asm;
    5
    6/// Full system is the required shareability domain, reads and writes are the
    7/// required access types
    8#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
    9pub struct SY;
    10
    11#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
    12impl super::super::sealed::Dmb for SY {
    13    #[inline(always)]
    14    unsafe fn __dmb(&self) {
    15        asm!(
    16            "mcr p15, 0, {}, c7, c10, 5",
    17            in(reg) 0_u32,
    18            options(preserves_flags, nostack)
    19        )
    20    }
    21}
    22
    23#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
    24impl super::super::sealed::Dsb for SY {
    25    #[inline(always)]
    26    unsafe fn __dsb(&self) {
    27        asm!(
    28            "mcr p15, 0, {}, c7, c10, 4",
    29            in(reg) 0_u32,
    30            options(preserves_flags, nostack)
    31        )
    32    }
    33}
    34
    35#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
    36impl super::super::sealed::Isb for SY {
    37    #[inline(always)]
    38    unsafe fn __isb(&self) {
    39        asm!(
    40            "mcr p15, 0, {}, c7, c5, 4",
    41            in(reg) 0_u32,
    42            options(preserves_flags, nostack)
    43        )
    44    }
    45}