#
core/stdarch/crates/core_arch/src/riscv64/
mod.rs

    1//! RISC-V RV64 specific intrinsics
    2use crate::arch::asm;
    3
    4mod zk;
    5
    6#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
    7pub use zk::*;
    8
    9/// Loads virtual machine memory by unsigned word integer
    10///
    11/// This instruction performs an explicit memory access as though `V=1`;
    12/// i.e., with the address translation and protection, and the endianness, that apply to memory
    13/// accesses in either VS-mode or VU-mode.
    14///
    15/// This operation is not available under RV32 base instruction set.
    16///
    17/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.WU`
    18/// instruction which is effectively a dereference to any memory address.
    19#[inline]
    20#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
    21pub unsafe fn hlv_wu(src: *const u32) -> u32 {
    22    let value: u32;
    23    asm!(".insn i 0x73, 0x4, {}, {}, 0x681", out(reg) value, in(reg) src, options(readonly, nostack));
    24    value
    25}
    26
    27/// Loads virtual machine memory by double integer
    28///
    29/// This instruction performs an explicit memory access as though `V=1`;
    30/// i.e., with the address translation and protection, and the endianness, that apply to memory
    31/// accesses in either VS-mode or VU-mode.
    32///
    33/// This operation is not available under RV32 base instruction set.
    34///
    35/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.D`
    36/// instruction which is effectively a dereference to any memory address.
    37#[inline]
    38#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
    39pub unsafe fn hlv_d(src: *const i64) -> i64 {
    40    let value: i64;
    41    asm!(".insn i 0x73, 0x4, {}, {}, 0x6C0", out(reg) value, in(reg) src, options(readonly, nostack));
    42    value
    43}
    44
    45/// Stores virtual machine memory by double integer
    46///
    47/// This instruction performs an explicit memory access as though `V=1`;
    48/// i.e., with the address translation and protection, and the endianness, that apply to memory
    49/// accesses in either VS-mode or VU-mode.
    50///
    51/// This function is unsafe for it accesses the virtual supervisor or user via a `HSV.D`
    52/// instruction which is effectively a dereference to any memory address.
    53#[inline]
    54#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
    55pub unsafe fn hsv_d(dst: *mut i64, src: i64) {
    56    asm!(".insn r 0x73, 0x4, 0x37, x0, {}, {}", in(reg) dst, in(reg) src, options(nostack));
    57}