ot on our read step and leave any new bits unaffected (at least that's what docs say). So if any new interrupts come up we won't miss it. I've tested this with an AR5213 and an AR2425 and it seems O.K. Many thanks to Adrian Chadd for debuging this and reviewing the patch ! v2: Make sure we don't clear PISR bits that map to SISR generated interrupts (added a comment on the code for this) Signed-off-by: Nick Kossifidis Signed-off-by: John W. Linville *x