2b41f7456223ba6abd3b38d7b54be97914f3aa5
author Will Deacon <will.deacon@arm.com> 1311111808 +0100
committer Will Deacon <will.deacon@arm.com> 1314782281 +0100

ARM: perf: index PMU registers from zero

ARM PMU code used to use 1-based indices for PMU registers. This caused
several data structures (pmu_hw_events::{active_events, used_mask, events})
to have an unused element at index zero. ARMPMU_MAX_HWEVENTS still takes
this indexing into account, and currently equates to 33.

This patch updates the core ARM perf code to use the 0th index again.

Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
ÔI	M›0x