c04a36a0a16f7da04 author Jesse Barnes 1318753411 +0200 committer Keith Packard 1319149601 -0700 drm/i915: Use PIPE_CONTROL for flushing on gen6+. v2 by danvet: Use a new flag to flush the render target cache on gen6+ (hw reuses the old write flush bit), as suggested by Ben Widawsdy. Signed-off-by: Jesse Barnes Signed-off-by: Kenneth Graunke [danvet: this seems to fix cairo-perf-trace hangs on my snb] Signed-Off-by: Daniel Vetter Signed-off-by: Keith Packard r-x