5e58accf141894f
parent edabd38e1a017e922e3e3b485ee3ddb4df433aa4
author Lennert Buytenhek <buytenh@marvell.com> 1259084032 +0200
committer Nicolas Pitre <nico@fluxnic.net> 1259354601 -0500

ARM: Add Tauros2 L2 cache controller support

Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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