rs/gpu/drm/amd/display/dc/dsc/dc_dsc.c:1161`
    - `min_slices_h = dc_fixpt_ceil(dc_fixpt_max(dc_fixpt_div_int(dc_fix
      pt_from_int(pic_width), dsc_common_caps.max_slice_width),
      dc_fixpt_from_int(min_slices_h)));`
    - This enforces `min_slices_h >= ceil(pic_width / max_slice_width)`,
      i.e., each slice width ≤ sink/source capability.
  - This is then snapped to a supported slice count:
    `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:1165`
    - `min_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps,
      min_slices_h);`
  - Throughput and divisibility constraints are applied after this in
    existing code: `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:1168`,
    `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:1177`.

- Why it matters: The final validation still checks `slice_width <=
  dsc_common_caps.max_slice_width` at
  `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:1236`. Before this patch,
  `min_slices_h` could be too low (because width wasn’t considered),
  leading to late failure and no attempt to raise the slice count if
  `policy.use_min_slices_h` is active (set to true in policy defaults:
  `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:1373`). By raising
  `min_slices_h` early to meet the width constraint, the algorithm
  avoids that false “not possible” outcome and finds a valid
  configuration when one exists.

- Correct intersection of caps: The code uses
  `dsc_common_caps.max_slice_width`, which is already the minimum
  between sink and encoder capabilities (intersection):
  `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:753`. This matches the
  commit’s intent to “take the valid minimum between the sink and
  source.”

- Consistent with existing logic elsewhere: A similar max-slice-width
  constraint is already considered when computing ODM-related minimum
  slices (`get_min_dsc_slice_count_for_odm`) via a width-based term:
  `drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c:664`. This patch brings
  the main DSC setup path into alignment with that established
  reasoning.

- Scope and risk:
  - Small and contained (a few lines in one function, one file).
  - No API/ABI changes, no architectural shifts.
  - Targets a correctness issue in AMD DC DSC slice selection.
  - Low risk of regression: it only increases the minimum slices to
    satisfy an already-known sink limitation; subsequent
    throughput/divisibility checks remain unchanged.

- User impact: Prevents display failures or inability to enable DSC on
  sinks that enforce max slice width, especially for high
  resolutions/refresh rates where DSC is required.

Given it’s a targeted regression fix, minimal risk, and improves
correctness for real hardware, this is a good candidate for stable
backporting.

 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 1f53a9f0c0ac3..e4144b2443324 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1157,6 +1157,11 @@ static bool setup_dsc_config(
 	if (!is_dsc_possible)
 		goto done;
 
+	/* increase miniumum slice count to meet sink slice width limitations */
+	min_slices_h = dc_fixpt_ceil(dc_fixpt_max(
+			dc_fixpt_div_int(dc_fixpt_from_int(pic_width), dsc_common_caps.max_slice_width), // sink min
+			dc_fixpt_from_int(min_slices_h))); // source min
+
 	min_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, min_slices_h);
 
 	/* increase minimum slice count to meet sink throughput limitations */
-- 
2.51.0[PATCH AUTOSEL 6.17] drm/amd/display: Consider sink max slice width limitation for dscSasha Levin <sashal@kernel.org> undefinedpatches@lists.linux.dev, stable@vger.kernel.org undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined�I��