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Wed, 25 Feb 2026 09:36:22 -0500 (EST) Date: Wed, 25 Feb 2026 06:36:13 -0800 From: Greg KH To: Thomas =?iso-8859-1?Q?Wei=DFschuh?= Cc: stable@vger.kernel.org, Matthew Wilcox , Linus Torvalds , Ben Hutchings Subject: Re: [PATCH 5.10.y 5.15.y 6.1.y 6.6.y 6.12.y 6.18.y 6.19.y] ARM: clean up the memset64() C wrapper Message-ID: <2026022546-sloping-proactive-d4f7@gregkh> References: <20260225-arm-memset64-stable-v1-1-f453c4933ca0@linutronix.de> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260225-arm-memset64-stable-v1-1-f453c4933ca0@linutronix.de> X-DKIM: signer='kroah.com' status='pass' reason='' DKIMCheck: Server passes DKIM test, 0 Spam score X-DKIM: signer='messagingengine.com' status='pass' reason='' X-Spam-Score: 0.4 (/) X-Spam-Report: Spam detection software, running on the system "witcher.mxrouting.net", has performed the tests listed below against this email. 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[172.105.105.114 listed in list.dnswl.org] 1.5 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different 0.0 URIBL_ZEN_BLOCKED_OPENDNS ADMINISTRATOR NOTICE: The query to zen.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [URIs: kroah.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.0 MAILING_LIST_MULTI Multiple indicators imply a widely-seen list manager SpamTally: Final spam score: 4 On Wed, Feb 25, 2026 at 12:35:09PM +0100, Thomas Weischuh wrote: > [ Upstream commit b52343d1cb47bb27ca32a3f4952cc2fd3cd165bf ] > > The current logic to split the 64-bit argument into its 32-bit halves is > byte-order specific and a bit clunky. Use a union instead which is > easier to read and works in all cases. > > GCC still generates the same machine code. > > While at it, rename the arguments of the __memset64() prototype to > actually reflect their semantics. > > Signed-off-by: Thomas Weischuh > Signed-off-by: Linus Torvalds > Reported-by: Ben Hutchings # for -stable > Link: https://lore.kernel.org/all/1a11526ae3d8664f705b541b8d6ea57b847b49a8.camel@decadent.org.uk/ > Suggested-by: https://lore.kernel.org/all/aZonkWMwpbFhzDJq@casper.infradead.org/ # for -stable > Link: https://lore.kernel.org/all/aZonkWMwpbFhzDJq@casper.infradead.org/ > --- > Hi stable team, > > unfortunately the backports of commit 23ea2a4c7232 ("ARM: 9468/1: fix > memset64() on big-endian") does not work on 5.10 and 5.15 as > CONFIG_CPU_LITTLE_ENDIAN does not exist there, effectively breaking memset64() > on little-endian. Please use this variant instead which always works. > For consistency I prefer to have it backported to all versions. > --- > arch/arm/include/asm/string.h | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h > index b5ad23acb303..369781ec5511 100644 > --- a/arch/arm/include/asm/string.h > +++ b/arch/arm/include/asm/string.h > @@ -33,13 +33,17 @@ static inline void *memset32(uint32_t *p, uint32_t v, __kernel_size_t n) > } > > #define __HAVE_ARCH_MEMSET64 > -extern void *__memset64(uint64_t *, uint32_t low, __kernel_size_t, uint32_t hi); > +extern void *__memset64(uint64_t *, uint32_t first, __kernel_size_t, uint32_t second); > static inline void *memset64(uint64_t *p, uint64_t v, __kernel_size_t n) > { > - if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) > - return __memset64(p, v, n * 8, v >> 32); > - else > - return __memset64(p, v >> 32, n * 8, v); > + union { > + uint64_t val; > + struct { > + uint32_t first, second; > + }; > + } word = { .val = v }; > + > + return __memset64(p, word.first, n * 8, word.second); > } > > #endif > > --- I don't understand, why is this patch needed at all? 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Information: https://docs.mxroute.com/docs/expert-spam-filtering.html --- Content analysis details: (0.4 points) --- pts rule name description ---- ---------------------- ----------------------------------------- 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block for more information. [URIs: intel.com] 0.0 URIBL_DBL_BLOCKED_OPENDNS ADMINISTRATOR NOTICE: The query to dbl.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [URIs: intel.com] 0.0 RCVD_IN_ZEN_BLOCKED_OPENDNS RBL: ADMINISTRATOR NOTICE: The query to zen.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [172.234.253.10 listed in zen.spamhaus.org] 1.5 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different 0.0 URIBL_ZEN_BLOCKED_OPENDNS ADMINISTRATOR NOTICE: The query to zen.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [URIs: intel.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.0 MAILING_LIST_MULTI Multiple indicators imply a widely-seen list manager -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender SpamTally: Final spam score: 4 On 2/25/2026 6:59 PM, Jani Nikula wrote: > On Wed, 25 Feb 2026, "Nautiyal, Ankit K" wrote: >> On 2/19/2026 6:37 PM, Jouni Högander wrote: >>> There is Selective Update slice row per frame and picture height >>> configurations needed on DSC when using Selective Update Early >>> Transport. Calculate and configure these when using Early Transport. >>> >>> Bspec: 68927 >>> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") >>> Cc: # v6.9+ >> >> This patch needs the other patch where registers are defined. I am not >> sure if stable will only pick this patch or will try to find out the >> dependency patch. >> >> We need to check if there is a way to tell the dependency patch/commit >> to stable, so that both patches are applied together. >> >> If we want this change to get ported to older kernels, we might need to >> squash the register definition patch with this patch. > Nope. Neither we nor stable want dependencies squashed. They'll happily > pick up extra dependency commits if needed, though. > > Someone(tm) just needs to let them know about the dependencies when they > send the mail about (the presumably failed) backport attempt. Got it :) thanks Jani. Regards, Ankit > > BR, > Jani. > > >> >>> Signed-off-by: Jouni Högander >>> --- >>> .../drm/i915/display/intel_display_types.h | 1 + >>> drivers/gpu/drm/i915/display/intel_psr.c | 24 +++++++++++++++++++ >>> 2 files changed, 25 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h >>> index e8e4af03a6a6..8903804c04b1 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h >>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h >>> @@ -1381,6 +1381,7 @@ struct intel_crtc_state { >>> u32 psr2_man_track_ctl; >>> >>> u32 pipe_srcsz_early_tpt; >>> + u32 dsc_su_parameter_set_0_calc; >> I think let's just have a bool parameter something like >> psr_su_update_dsc_pps. >> >> We can set this bool variable during intel_psr2_sel_fetch_update() >> >> >>> >>> struct drm_rect psr2_su_area; >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c >>> index 331645a2c9f6..0a2948ec308d 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_psr.c >>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c >>> @@ -2618,6 +2618,11 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, >>> >>> intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), >>> crtc_state->pipe_srcsz_early_tpt); >>> + intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC0(crtc->pipe), >>> + crtc_state->dsc_su_parameter_set_0_calc); >>> + if (intel_dsc_get_vdsc_per_pipe(crtc_state) > 1) >>> + intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC1(crtc->pipe), >>> + crtc_state->dsc_su_parameter_set_0_calc); >>> } >>> >>> static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, >>> @@ -2668,6 +2673,23 @@ static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, >>> return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); >>> } >>> >>> +static u32 psr2_dsc_su_parameter_set_0_calc(struct intel_crtc_state *crtc_state, >>> + bool full_update) >>> +{ >>> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >>> + int slice_row_per_frame, pic_height; >>> + >>> + if (!crtc_state->enable_psr2_su_region_et || full_update || >>> + !crtc_state->dsc.compression_enable) >>> + return 0; >>> + >> Although we are making sure that height of the psr2_su_area is a >> multiple of the slice_height, perhaps it would be good to have a >> drm_WARN here to flag any misconfiguration i.e. if height is not a >> multiple of slice_height. >> >> >>> + slice_row_per_frame = drm_rect_height(&crtc_state->psr2_su_area) / vdsc_cfg->slice_height; >>> + pic_height = slice_row_per_frame * vdsc_cfg->slice_height; >>> + >>> + return DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame) | >>> + DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(pic_height); >>> +} >> Since this writes a DSC register belonging to PPS Set 0, this function >> should be moved to intel_vdsc.c. >> >> Also, based on the boolean flag (psr_su_update_dsc_pps) discussed above, >> this function should simply retrieve the required fields from crtc_state >> and program the register. >> >> Such a helper function should then be called from >> intel_psr2_program_trans_man_trk_ctl() in place of the direct >> intel_reg_write() call. >> >> IMO, all register reads/writes, along with the wrappers/helpers around >> them, should live in the file corresponding to the block that owns those >> registers, based on context. >> >> >> Regards, >> >> Ankit >> >>> + >>> static void clip_area_update(struct drm_rect *overlap_damage_area, >>> struct drm_rect *damage_area, >>> struct drm_rect *pipe_src) >>> @@ -3026,6 +3048,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, >>> psr2_man_trk_ctl_calc(crtc_state, full_update); >>> crtc_state->pipe_srcsz_early_tpt = >>> psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); >>> + crtc_state->dsc_su_parameter_set_0_calc = psr2_dsc_su_parameter_set_0_calc(crtc_state, >>> + full_update); >>> return 0; >>> } >>> From - Wed Feb 25 14:36:47 2026 X-Mozilla-Status: 0001 X-Mozilla-Status2: 00000000 Return-Path: Delivered-To: hi@josie.lol Received: from witcher.mxrouting.net by witcher.mxrouting.net with LMTP id KJeWL/kIn2nV/QcAYBR5ng (envelope-from ) for ; Wed, 25 Feb 2026 14:36:41 +0000 Return-path: Envelope-to: hi@josie.lol Delivery-date: Wed, 25 Feb 2026 14:36:41 +0000 Received: from tor.lore.kernel.org ([172.105.105.114]) by witcher.mxrouting.net with esmtps (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98) (envelope-from ) id 1vvG0H-00000002CJU-0pP1 for hi@josie.lol; Wed, 25 Feb 2026 14:36:41 +0000 Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id BC2BF301877B for ; Wed, 25 Feb 2026 14:36:40 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DFA903AEF54; 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Wed, 25 Feb 2026 06:36:36 -0800 (PST) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260225012348.915798704@linuxfoundation.org> In-Reply-To: <20260225012348.915798704@linuxfoundation.org> From: Jeffrin Thalakkottoor Date: Wed, 25 Feb 2026 20:05:59 +0530 X-Gm-Features: AaiRm51dFPxFAjtNDltCSh9T-PORoFUyIe-AxoTdzJjCL4PMD3axwmNmKN25HEs Message-ID: Subject: Re: [PATCH 6.18 000/641] 6.18.14-rc1 review To: Greg Kroah-Hartman , "Tested-by: Jeffrin Jose T" Cc: stable@vger.kernel.org, patches@lists.linux.dev, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, akpm@linux-foundation.org, linux@roeck-us.net, shuah@kernel.org, patches@kernelci.org, lkft-triage@lists.linaro.org, pavel@nabladev.com, jonathanh@nvidia.com, f.fainelli@gmail.com, sudipm.mukherjee@gmail.com, rwarsow@gmx.de, conor@kernel.org, hargar@microsoft.com, broonie@kernel.org, achill@achill.org, sr@sladewatkins.com Content-Type: text/plain; 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Information: https://docs.mxroute.com/docs/expert-spam-filtering.html --- Content analysis details: (0.4 points) --- pts rule name description ---- ---------------------- ----------------------------------------- 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block for more information. [URIs: nvidia.com] 0.0 URIBL_DBL_BLOCKED_OPENDNS ADMINISTRATOR NOTICE: The query to dbl.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [URIs: nvidia.com] 0.0 RCVD_IN_ZEN_BLOCKED_OPENDNS RBL: ADMINISTRATOR NOTICE: The query to zen.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [172.105.105.114 listed in zen.spamhaus.org] 0.0 RCVD_IN_DNSWL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to DNSWL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#DnsBlocklists-dnsbl-block for more information. [172.105.105.114 listed in list.dnswl.org] 1.5 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different 0.0 URIBL_ZEN_BLOCKED_OPENDNS ADMINISTRATOR NOTICE: The query to zen.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [URIs: nvidia.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.0 MAILING_LIST_MULTI Multiple indicators imply a widely-seen list manager -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender SpamTally: Final spam score: 4 On 19.02.26 22:26, Ionut Nechita (Wind River) wrote: > From: Ionut Nechita > > After reverting commit 05703271c3cd ("PCI/IOV: Add PCI rescan-remove > locking when enabling/disabling SR-IOV") and moving the lock to > sriov_numvfs_store(), the path through driver .remove() (e.g. rmmod, > or manual unbind) that calls pci_disable_sriov() directly remains > unprotected against concurrent hotplug events. This affects any SR-IOV > capable driver that calls pci_disable_sriov() from its .remove() > callback (i40e, ice, mlx5, bnxt, etc.). > > On s390, platform-generated hot-unplug events for VFs can race with > sriov_del_vfs() when a PF driver is being unloaded. The platform event > handler takes pci_rescan_remove_lock, but sriov_del_vfs() does not, > leading to double removal and list corruption. > > We cannot use a plain mutex_lock() here because sriov_del_vfs() may also > be called from paths that already hold pci_rescan_remove_lock (e.g. > remove_store -> pci_stop_and_remove_bus_device_locked, or > sriov_numvfs_store with the lock taken by the previous patch). Using > mutex_lock() in those cases would deadlock. > > Instead, introduce owner tracking for pci_rescan_remove_lock via a new > pci_lock_rescan_remove_reentrant() helper. This function checks if the > current task already holds the lock: > - If the lock is not held: acquires it and returns true, providing > full serialization against concurrent hotplug events (including > platform-generated events on s390). > - If the lock is already held by the current task (reentrant call from > remove_store or sriov_numvfs_store paths): returns false without > re-acquiring, avoiding deadlock while the caller already provides > the necessary serialization. > - If the lock is held by another task (concurrent hotplug): blocks > until the lock is released, then acquires it, providing complete > serialization. This is the key improvement over a trylock approach. > > A matching pci_unlock_rescan_remove_reentrant() helper takes the return > value of the lock function as argument, so callers don't need to > open-code the conditional unlock. > > The "reentrant" naming is chosen to avoid confusion with existing > mutex_lock_nested() which is a lockdep annotation concept, not actual > reentrant locking. > > Note: owner-tracking patterns for reentrant lock behavior exist elsewhere > in the kernel, for example in the regulator core (drivers/regulator/core.c) > with rdev->mutex_owner, and in the PPP subsystem (drivers/net/ppp/ > ppp_generic.c) with xmit_recursion->owner. > > The declarations are placed in include/linux/pci.h alongside the existing > pci_lock_rescan_remove()/pci_unlock_rescan_remove() declarations to > maintain API consistency and allow use by external drivers if needed. > > Fixes: 18f9e9d150fc ("PCI/IOV: Factor out sriov_add_vfs()") > Cc: stable@vger.kernel.org > Signed-off-by: Ionut Nechita > Signed-off-by: Ionut Nechita Thanks! According to [1]: Tested-by: Dragos Tatulea [1] https://lore.kernel.org/linux-pci/a02222aa-64a2-43b9-86f3-a31b4668206c@nvidia.com/ Thanks, Dragos From - Wed Feb 25 18:44:06 2026 X-Mozilla-Status: 0001 X-Mozilla-Status2: 00000000 Return-Path: Delivered-To: hi@josie.lol Received: from witcher.mxrouting.net by witcher.mxrouting.net with LMTP id CJjhHvFCn2kIZiUAYBR5ng (envelope-from ) for ; Wed, 25 Feb 2026 18:44:01 +0000 Return-path: Envelope-to: hi@josie.lol Delivery-date: Wed, 25 Feb 2026 18:44:01 +0000 Received: from sea.lore.kernel.org ([172.234.253.10]) by witcher.mxrouting.net with esmtps (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98) (envelope-from ) id 1vvJrc-0000000AM8i-3OEW for hi@josie.lol; Wed, 25 Feb 2026 18:44:01 +0000 Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 4B0CC30115A0 for ; Wed, 25 Feb 2026 18:43:08 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 843343B8BA7; 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[172.234.253.10 listed in list.dnswl.org] 1.5 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 URIBL_ZEN_BLOCKED_OPENDNS ADMINISTRATOR NOTICE: The query to zen.spamhaus.org was blocked due to usage of an open resolver. See https://www.spamhaus.org/returnc/pub/ [URIs: intel.com] -1.0 MAILING_LIST_MULTI Multiple indicators imply a widely-seen list manager -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender SpamTally: Final spam score: 4 On 2/24/2026 4:11 PM, Jakub Kicinski wrote: > On Tue, 24 Feb 2026 14:59:36 -0800 Tony Nguyen wrote: >> Yea, looks like we need to do some adjustments here. Also, the AI review >> I just ran on this is reporting another issue that we'll need to look >> into. I'm going to drop this one from the series to not hold the others >> up on this. > > I'd sometimes apply series partially for y'all but FWIW the idpf > "defensive programming instead of proper rollback" patches really > don't make me want to interact with this series more than I have to. > You don't have to rework them. Just expect some delays, I guess. Hi Jakub, Yea, when we reviewed them, we tried to come up with a solution to suggest that wouldn't need the added checks but couldn't come up with anything that wouldn't require large amounts of changes/refactoring. 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