e) to MODE. */ #define X87_ENABLE_FLOAT(MODE, IMODE) \ (ix86_unsafe_math_optimizations \ || ix86_excess_precision == EXCESS_PRECISION_FAST \ || (MODE) == XFmode \ || ((MODE) == DFmode && (IMODE) == SImode) \ || (IMODE) == HImode) /* target machine storage layout */ #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) #define LONG_LONG_TYPE_SIZE 64 #define WIDEST_HARDWARE_FP_SIZE 80 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT #define MAX_BITS_PER_WORD 64 #else #define MAX_BITS_PER_WORD 32 #endif /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the 80386. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is not true on the 80386. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is the lowest numbered. */ /* Not true for 80386 */ #define WORDS_BIG_ENDIAN 0 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) #ifndef IN_LIBGCC2 #define MIN_UNITS_PER_WORD 4 #endif /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY BITS_PER_WORD /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) /* Stack boundary of the main function guaranteed by OS. */ #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) /* Minimum stack boundary. */ #define MIN_STACK_BOUNDARY BITS_PER_WORD /* Boundary (in *bits*) on which the stack pointer prefers to be aligned; the compiler cannot rely on having this alignment. */ #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for both 32bit and 64bit, to support codes that need 128 bit stack alignment for SSE instructions, but can't realign the stack. */ #define PREFERRED_STACK_BOUNDARY_DEFAULT \ (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) /* 1 if -mstackrealign should be turned on by default. It will generate an alternate prologue and epilogue that realigns the runtime stack if nessary. This supports mixing codes that keep a 4-byte aligned stack, as specified by i386 psABI, with codes that need a 16-byte aligned stack, as required by SSE instructions. */ #define STACK_REALIGN_DEFAULT 0 /* Boundary (in *bits*) on which the incoming stack is aligned. */ #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary /* According to Windows x64 software convention, the maximum stack allocatable in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of instructions allowed to adjust the stack pointer in the epilog, forcing the use of frame pointer for frames larger than 2 GB. This theorical limit is reduced by 256, an over-estimated upper bound for the stack use by the prologue. We define only one threshold for both the prolog and the epilog. When the frame size is larger than this threshold, we allocate the area to save SSE regs, then save them, and then allocate the remaining. There is no SEH unwind info for this later allocation. */ #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is mandatory for the 64-bit ABI, and may or may not be true for other operating systems. */ #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT /* Minimum allocation boundary for the code of a function. */ #define FUNCTION_BOUNDARY 8 /* We will and with this value to test if a custom function descriptor needs a static chain. The function boundary must the adjusted so that the bit this represents is no longer part of the address. 0 Disables the custom function descriptors. */ #define X86_CUSTOM_FUNCTION_TEST 1 /* C++ stores the virtual bit in the lowest bit of function pointers. */ #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn /* Minimum size in bits of the largest boundary to which any and all fundamental data types supported by the hardware might need to be aligned. No data type wants to be aligned rounder than this. Pentium+ prefers DFmode values to be aligned to 64 bit boundary and Pentium Pro XFmode values at 128 bit boundaries. When increasing the maximum, also update TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ #define BIGGEST_ALIGNMENT \ (TARGET_IAMCU ? 32 : ((TARGET_AVX512F && TARGET_EVEX512) \ ? 512 : (TARGET_AVX ? 256 : 128))) /* Maximum stack alignment. */ #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT /* Alignment value for attribute ((aligned)). It is a constant since it is the part of the ABI. We shouldn't change it with -mavx. */ #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) /* Decide whether a variable of mode MODE should be 128 bit aligned. */ #define ALIGN_MODE_128(MODE) \ ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) /* The published ABIs say that doubles should be aligned on word boundaries, so lower the alignment for structure fields unless -malign-double is set. */ /* ??? Blah -- this macro is used directly by libobjc. Since it supports no vector modes, cut out the complexity and fall back on BIGGEST_FIELD_ALIGNMENT. */ #ifdef IN_TARGET_LIBS #ifdef __x86_64__ #define BIGGEST_FIELD_ALIGNMENT 128 #else #define BIGGEST_FIELD_ALIGNMENT 32 #endif #else #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ x86_field_alignment ((TYPE), (COMPUTED)) #endif /* If defined, a C expression to compute the alignment for a static variable. TYPE is the data type, and ALIGN is the alignment that the object would ordinarily have. The value of this macro is used instead of that alignment to align the object. If this macro is not defined, then ALIGN is used. One use of this macro is to increase alignment of medium-size data to make it all fit in fewer cache lines. Another is to cause character arrays to be word-aligned so that `strcpy' calls that copy constants to character arrays can be done inline. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ ix86_data_alignment ((TYPE), (ALIGN), true) /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates some alignment increase, instead of optimization only purposes. E.g. AMD x86-64 psABI says that variables with array type larger than 15 bytes must be aligned to 16 byte boundaries. If this macro is not defined, then ALIGN is used. */ #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ ix86_data_alignment ((TYPE), (ALIGN), false) /* If defined, a C expression to compute the alignment for a local variable. TYPE is the data type, and ALIGN is the alignment that the object would ordinarily have. The value of this macro is used instead of that alignment to align the object. If this macro is not defined, then ALIGN is used. One use of this macro is to increase alignment of medium-size data to make it all fit in fewer cache lines. */ #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) /* If defined, a C expression to compute the alignment for stack slot. TYPE is the data type, MODE is the widest mode available, and ALIGN is the alignment that the slot would ordinarily have. The value of this macro is used instead of that alignment to align the slot. If this macro is not defined, then ALIGN is used when TYPE is NULL, Otherwise, LOCAL_ALIGNMENT will be used. One use of this macro is to set alignment of stack slot to the maximum alignment of all possible modes which the slot may have. */ #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ ix86_local_alignment ((TYPE), (MODE), (ALIGN)) /* If defined, a C expression to compute the alignment for a local variable DECL. If this macro is not defined, then LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. One use of this macro is to increase alignment of medium-size data to make it all fit in fewer cache lines. */ #define LOCAL_DECL_ALIGNMENT(DECL) \ ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) /* If defined, a C expression to compute the minimum required alignment for dynamic stack realignment purposes for EXP (a TYPE or DECL), MODE, assuming normal alignment ALIGN. If this macro is not defined, then (ALIGN) will be used. */ #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 /* If bit field type is int, don't let it cross an int, and give entire struct the alignment of an int. */ /* Required on the 386 since it doesn't have bit-field insns. */ #define PCC_BITFIELD_TYPE_MATTERS 1 #define VECTOR_STORE_FLAG_VALUE(MODE) \ (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX) /* Standard register usage. */ /* This processor has special stack-like registers. See reg-stack.cc for details. */ #define STACK_REGS #define IS_STACK_MODE(MODE) \ (X87_FLOAT_MODE_P (MODE) \ && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ || TARGET_MIX_SSE_I387)) /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. In the 80386 we give the 8 general purpose registers the numbers 0-7. We number the floating point registers 8-15. Note that registers 0-7 can be accessed as a short or int, while only 0-3 may be used with byte `mov' instructions. Reg 16 does not correspond to any hardware register, but instead appears in the RTL as an argument pointer prior to reload, and is eliminated during reloading in favor of either the stack or frame pointer. */ #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG /* Number of hardware registers that go into the DWARF-2 unwind info. If not defined, equals FIRST_PSEUDO_REGISTER. */ #define DWARF_FRAME_REGISTERS 17 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the 80386, the stack pointer is such, as is the arg pointer. REX registers are disabled for 32bit targets in TARGET_CONDITIONAL_REGISTER_USAGE. */ #define FIXED_REGISTERS \ /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ /*arg,flags,fpsr,frame*/ \ 1, 1, 1, 1, \ /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* r16, r17, r18, r19, r20, r21, r22, r23*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* r24, r25, r26, r27, r28, r29, r30, r31*/ \ 0, 0, 0, 0, 0, 0, 0, 0} \ /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. Value is set to 1 if the register is call used unconditionally. Bit one is set if the register is call used on TARGET_32BIT ABI. Bit two is set if the register is call used on TARGET_64BIT ABI. Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) #define CALL_USED_REGISTERS \ /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ /*arg,flags,fpsr,frame*/ \ 1, 1, 1, 1, \ /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1, 1, 1, 1, 1, 1, 6, 6, \ /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1, 1, 1, 1, 2, 2, 2, 2, \ /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 6, 6, 6, 6, 6, 6, 6, 6, \ /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* r16, r17, r18, r19, r20, r21, r22, r23*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* r24, r25, r26, r27, r28, r29, r30, r31*/ \ 1, 1, 1, 1, 1, 1, 1, 1} \ /* Order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. List frame pointer late and fixed registers last. Note that, in general, we prefer registers listed in CALL_USED_REGISTERS, keeping the others available for storage of persistent values. The ADJUST_REG_ALLOC_ORDER actually overwrite the order, so this is just empty initializer for array. */ #define REG_ALLOC_ORDER \ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91} /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order to be rearranged based on a particular function. When using sse math, we want to allocate SSE before x87 registers and vice versa. */ #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () #define INSN_BASE_REG_CLASS(INSN) \ ix86_insn_base_reg_class (INSN) #define REGNO_OK_FOR_INSN_BASE_P(NUM, INSN) \ ix86_regno_ok_for_insn_base_p (NUM, INSN) #define INSN_INDEX_REG_CLASS(INSN) \ ix86_insn_index_reg_class (INSN) #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ && GENERAL_REGNO_P (REGNO) \ && ((MODE) == XFmode || (MODE) == XCmode)) #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) #define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE) #define VALID_AVX256_REG_MODE(MODE) \ ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ || (MODE) == V4DFmode || (MODE) == V16HFmode || (MODE) == V16BFmode) #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) #define VALID_AVX512F_SCALAR_MODE(MODE) \ ((MODE) == DImode || (MODE) == DFmode \ || (MODE) == SImode || (MODE) == SFmode \ || (MODE) == HImode || (MODE) == HFmode || (MODE) == BFmode) #define VALID_AVX512F_REG_MODE(MODE) \ ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ || (MODE) == V4TImode || (MODE) == V32HFmode || (MODE) == V32BFmode) #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) #define VALID_AVX512VL_128_REG_MODE(MODE) \ ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ || (MODE) == TFmode || (MODE) == V1TImode || (MODE) == V8HFmode \ || (MODE) == V8BFmode || (MODE) == TImode) #define VALID_AVX512FP16_REG_MODE(MODE) \ ((MODE) == V8HFmode || (MODE) == V16HFmode || (MODE) == V32HFmode) #define VALID_SSE2_TYPE_MODE(MODE) \ ((MODE) == HFmode || (MODE) == BFmode \ || (MODE) == HCmode || (MODE) == BCmode) #define VALID_SSE2_REG_MODE(MODE) \ ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ || (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \ || (MODE) == V8BFmode || (MODE) == V4BFmode || (MODE) == V2BFmode \ || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \ || (MODE) == V2DImode || (MODE) == V2QImode || (MODE) == HImode \ || (MODE) == DFmode || (MODE) == DImode \ || (MODE) == HFmode || (MODE) == BFmode) #define VALID_SSE_REG_MODE(MODE) \ ((MODE) == V1TImode || (MODE) == TImode \ || (MODE) == V4SFmode || (MODE) == V4SImode \ || (MODE) == SFmode || (MODE) == SImode \ || (MODE) == TFmode || (MODE) == TDmode) #define VALID_MMX_REG_MODE_3DNOW(MODE) \ ((MODE) == V2SFmode || (MODE) == SFmode) /* To match ia32 psABI, V4HFmode should be added here. */ #define VALID_MMX_REG_MODE(MODE) \ ((MODE) == V1DImode || (MODE) == DImode \ || (MODE) == V2SImode || (MODE) == SImode \ || (MODE) == V4HImode || (MODE) == V8QImode \ || (MODE) == V4HFmode || (MODE) == V4BFmode) #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) #define VALID_FP_MODE_P(MODE) \ ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) #define VALID_INT_MODE_P(MODE) \ ((MODE) == QImode || (MODE) == HImode \ || (MODE) == SImode || (MODE) == DImode \ || (MODE) == CQImode || (MODE) == CHImode \ || (MODE) == CSImode || (MODE) == CDImode \ || (MODE) == SDmode || (MODE) == DDmode \ || (MODE) == HFmode || (MODE) == HCmode || (MODE) == BFmode \ || (MODE) == V2HImode || (MODE) == V2HFmode || (MODE) == V2BFmode \ || (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \ || (TARGET_64BIT \ && ((MODE) == TImode || (MODE) == CTImode \ || (MODE) == TFmode || (MODE) == TCmode \ || (MODE) == V8QImode || (MODE) == V4HImode \ || (MODE) == V2SImode || (MODE) == TDmode))) /* Return true for modes passed in SSE registers. */ #define SSE_REG_MODE_P(MODE) \ ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ || (MODE) == V16SFmode \ || (MODE) == V32HFmode || (MODE) == V16HFmode || (MODE) == V8HFmode \ || (MODE) == V32BFmode || (MODE) == V16BFmode || (MODE) == V8BFmode) #define X87_FLOAT_MODE_P(MODE) \ (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) #define SSE_FLOAT_MODE_P(MODE) \ ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) #define SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P(MODE) \ ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ || (TARGET_AVX512FP16 && (MODE) == HFmode) \ || (TARGET_AVX10_2 && (MODE) == BFmode)) #define FMA4_VEC_FLOAT_MODE_P(MODE) \ (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ || (MODE) == V8SFmode || (MODE) == V4DFmode)) #define VALID_BCST_MODE_P(MODE) \ ((MODE) == SFmode || (MODE) == DFmode \ || (MODE) == SImode || (MODE) == DImode \ || (MODE) == HFmode) /* It is possible to write patterns to move flags; but until someone does it, */ #define AVOID_CCMODE_COPIES /* Specify the modes required to caller save a given hard regno. We do this on i386 to prevent flags from being saved at all. Kill any attempts to combine saving of modes. */ #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ (CC_REGNO_P (REGNO) ? VOIDmode \ : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \ : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ && TARGET_PARTIAL_REG_STALL) \ || MASK_REGNO_P (REGNO)) ? SImode \ : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ || MASK_REGNO_P (REGNO)) ? SImode \ : (MODE)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* on the 386 the pc register is %eip, and is not usable as a general register. The ordinary mov instructions won't work */ /* #define PC_REGNUM */ /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM ARGP_REG /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM SP_REG /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM FRAME_REG #define HARD_FRAME_POINTER_REGNUM BP_REG #define FIRST_INT_REG AX_REG #define LAST_INT_REG SP_REG #define FIRST_INDEX_REG AX_REG #define LAST_INDEX_REG BP_REG #define FIRST_QI_REG AX_REG #define LAST_QI_REG BX_REG /* First & last stack-like regs */ #define FIRST_STACK_REG ST0_REG #define LAST_STACK_REG ST7_REG #define FIRST_SSE_REG XMM0_REG #define LAST_SSE_REG XMM7_REG #define FIRST_MMX_REG MM0_REG #define LAST_MMX_REG MM7_REG #define FIRST_REX_INT_REG R8_REG #define LAST_REX_INT_REG R15_REG #define FIRST_REX_SSE_REG XMM8_REG #define LAST_REX_SSE_REG XMM15_REG #define FIRST_EXT_REX_SSE_REG XMM16_REG #define LAST_EXT_REX_SSE_REG XMM31_REG #define FIRST_MASK_REG MASK0_REG #define LAST_MASK_REG MASK7_REG #define FIRST_REX2_INT_REG R16_REG #define LAST_REX2_INT_REG R31_REG /* Override this in other tm.h files to cope with various OS lossage requiring a frame pointer. */ #ifndef SUBTARGET_FRAME_POINTER_REQUIRED #define SUBTARGET_FRAME_POINTER_REQUIRED 0 #endif /* Define the shadow offset for asan. Other OS's can override in the respective tm.h files. */ #ifndef SUBTARGET_SHADOW_OFFSET #define SUBTARGET_SHADOW_OFFSET \ (TARGET_LP64 ? HOST_WIDE_INT_C (0x7fff8000) : HOST_WIDE_INT_1 << 29) #endif /* Make sure we can access arbitrary call frames. */ #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () /* Register to hold the addressing base for position independent code access to data items. We don't use PIC pointer for 64bit mode. Define the regnum to dummy value to prevent gcc from pessimizing code dealing with EBX. To avoid clobbering a call-saved register unnecessarily, we renumber the pic register when possible. The change is visible after the prologue has been emitted. */ #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) #define PIC_OFFSET_TABLE_REGNUM \ (ix86_use_pseudo_pic_reg () \ ? (pic_offset_table_rtx \ ? INVALID_REGNUM \ : REAL_PIC_OFFSET_TABLE_REGNUM) \ : INVALID_REGNUM) #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" /* This is overridden by . */ #define MS_AGGREGATE_RETURN 0 #define KEEP_AGGREGATE_RETURN_POINTER 0