/***************************************************************************** * * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * * Neither the name of the copyright holders nor the names of * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #ifndef _AVR_ATA5795_H_INCLUDED #define _AVR_ATA5795_H_INCLUDED #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "ioa5795.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDRB7 7 // Inserted "DDB7" from "DDRB7" due to compatibility #define DDB7 7 #define DDRB6 6 // Inserted "DDB6" from "DDRB6" due to compatibility #define DDB6 6 #define DDRB5 5 // Inserted "DDB5" from "DDRB5" due to compatibility #define DDB5 5 #define DDRB4 4 // Inserted "DDB4" from "DDRB4" due to compatibility #define DDB4 4 #define DDRB3 3 // Inserted "DDB3" from "DDRB3" due to compatibility #define DDB3 3 #define DDRB2 2 // Inserted "DDB2" from "DDRB2" due to compatibility #define DDB2 2 #define DDRB1 1 // Inserted "DDB1" from "DDRB1" due to compatibility #define DDB1 1 #define DDRB0 0 // Inserted "DDB0" from "DDRB0" due to compatibility #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PORTB7 7 #define PORTB6 6 #define PORTB5 5 #define PORTB4 4 #define PORTB3 3 #define PORTB2 2 #define PORTB1 1 #define PORTB0 0 #define PINC _SFR_IO8(0x06) #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDRC4 4 // Inserted "DDC4" from "DDRC4" due to compatibility #define DDC4 4 #define DDRC3 3 // Inserted "DDC3" from "DDRC3" due to compatibility #define DDC3 3 #define DDRC2 2 // Inserted "DDC2" from "DDRC2" due to compatibility #define DDC2 2 #define DDRC1 1 // Inserted "DDC1" from "DDRC1" due to compatibility #define DDC1 1 #define DDRC0 0 // Inserted "DDC0" from "DDRC0" due to compatibility #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PORTC4 4 #define PORTC3 3 #define PORTC2 2 #define PORTC1 1 #define PORTC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDRD7 7 // Inserted "DDD7" from "DDRD7" due to compatibility #define DDD7 7 #define DDRD6 6 // Inserted "DDD6" from "DDRD6" due to compatibility #define DDD6 6 #define DDRD5 5 // Inserted "DDD5" from "DDRD5" due to compatibility #define DDD5 5 #define DDRD4 4 // Inserted "DDD4" from "DDRD4" due to compatibility #define DDD4 4 #define DDRD3 3 // Inserted "DDD3" from "DDRD3" due to compatibility #define DDD3 3 #define DDRD2 2 // Inserted "DDD2" from "DDRD2" due to compatibility #define DDD2 2 #define DDRD1 1 // Inserted "DDD1" from "DDRD1" due to compatibility #define DDD1 1 #define DDRD0 0 // Inserted "DDD0" from "DDRD0" due to compatibility #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PORTD7 7 #define PORTD6 6 #define PORTD5 5 #define PORTD4 4 #define PORTD3 3 #define PORTD2 2 #define PORTD1 1 #define PORTD0 0 /* Reserved [0x0C] */ #define TPCR _SFR_IO8(0x0D) #define TPMA 0 #define TPMOD 1 #define TPMS0 2 #define TPMS1 3 #define TPMD0 4 #define TPMD1 5 #define TPPSD 6 #define TPD 7 #define TPFR _SFR_IO8(0x0E) #define TPF 0 #define TPA 1 #define TPGAP 2 #define TPPSW 3 #define CMCR _SFR_IO8(0x0F) #define CMM0 0 #define CMM1 1 #define SRCD 2 #define CO32D 3 #define CCS 4 #define ECINS 5 #define CMONEN 6 #define CMCCE 7 #define CMSR _SFR_IO8(0x10) #define ECF 0 #define SXF 1 #define RTCF 2 #define T2CR _SFR_IO8(0x11) #define T2OTM 0 #define T2CTM 1 #define T2CRM 2 #define T2GRM 3 #define T2TOP 4 #define T2RES 5 #define T2TS 6 #define T2E 7 #define T3CR _SFR_IO8(0x12) #define T3OTM 0 #define T3CTM 1 #define T3CRM 2 #define T3CPRM 3 #define T3TOP 4 #define T3RES 5 #define T3CPTM 6 #define T3E 7 #define AESCR _SFR_IO8(0x13) #define AESWK 0 #define AESWD 1 #define AESIM 2 #define AESD 3 #define AESXOR 4 #define AESRES 5 #define AESE 7 #define AESSR _SFR_IO8(0x14) #define AESRF 0 #define AESERF 7 #define TMIFR _SFR_IO8(0x15) #define TMRXF 0 #define TMTXF 1 #define TMTCF 2 #define TMRXS 3 #define TMTXS 4 #define VMSR _SFR_IO8(0x16) #define VMF 0 #define PCIFR _SFR_IO8(0x17) #define PCIF0 0 #define PCIF1 1 /* Reserved [0x18] */ #define T0IFR _SFR_IO8(0x19) #define T0F 0 #define T1IFR _SFR_IO8(0x1A) #define T1F 0 #define T2IFR _SFR_IO8(0x1B) #define T2OFF 0 #define T2COF 1 #define T3IFR _SFR_IO8(0x1C) #define T3OFF 0 #define T3COF 1 #define T3ICF 2 #define EIFR _SFR_IO8(0x1D) #define INTF0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EELP 6 #define EEDR _SFR_IO8(0x20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) #define EEPR _SFR_IO8(0x23) #define EEAP0 0 #define EEAP1 1 #define EEAP2 2 #define EEAP3 3 #define EECCR _SFR_IO8(0x24) #define EEL0 0 #define EEL1 1 #define EEL2 2 #define EEL3 3 /* Reserved [0x25] */ #define PCICR _SFR_IO8(0x26) #define PCIE0 0 #define PCIE1 1 #define EIMSK _SFR_IO8(0x27) #define INT0 0 #define TMDR _SFR_IO8(0x28) #define AESDR _SFR_IO8(0x29) #define AESKR _SFR_IO8(0x2A) #define AESKR0 0 #define AESKR1 1 #define AESKR2 2 #define AESKR3 3 #define AESKR4 4 #define AESKR5 5 #define AESKR6 6 #define AESKR7 7 #define VMCR _SFR_IO8(0x2B) #define VMLS0 0 #define VMLS1 1 #define VMLS2 2 #define VMLS3 3 #define VMIM 4 #define VMPS 5 #define BODPD 6 #define BODLS 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) /* Reserved [0x2F..0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define TPRF 5 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define T1CR _SFR_IO8(0x38) #define T1PS0 0 #define T1PS1 1 #define T1IE 2 #define T1CS0 3 #define T1CS1 4 #define T1E 7 #define T0CR _SFR_IO8(0x39) #define T0PS0 0 #define T0PS1 1 #define T0PS2 2 #define T0IE 3 #define T0PR 4 /* Reserved [0x3A] */ #define CMIMR _SFR_IO8(0x3B) #define ECIE 0 #define SXIE 1 #define RTCIE 2 #define CLKPR _SFR_IO8(0x3C) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLTPS0 3 #define CLTPS1 4 #define CLTPS2 5 #define CLKPCE 7 /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDPS0 0 #define WDPS1 1 #define WDPS2 2 #define WDE 3 #define WDCE 4 /* Reserved [0x61..0x62] */ #define PRR0 _SFR_MEM8(0x63) #define PRT1 1 #define PRT2 2 #define PRT3 3 #define PRTM 4 #define PRCU 5 #define PRDS 6 #define PRVM 7 #define __AVR_HAVE_PRR0 ((1<