/* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */ /* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ #ifndef _AVR_IOM128RFA1_H_ #define _AVR_IOM128RFA1_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom128rfa1.h" #else # error "Attempt to include more than one file." #endif #include #ifndef __ASSEMBLER__ # define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) # define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) # define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) #endif /* __ASSEMBLER__ */ /* * USAGE: * * simple register assignment: * TIFR1 = 0x17 * subregister assignment: * TIFR1_struct.ocf1a = 1 * (subregister names are converted to small letters) */ /* Port A Input Pins Address */ #define PINA _SFR_IO8(0x00) /* PINA */ #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 /* Port A Data Direction Register */ #define DDRA _SFR_IO8(0x01) /* DDRA */ #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 /* Port A Data Register */ #define PORTA _SFR_IO8(0x02) /* PORTA */ #define PORTA0 0 #define PA0 0 #define PORTA1 1 #define PA1 1 #define PORTA2 2 #define PA2 2 #define PORTA3 3 #define PA3 3 #define PORTA4 4 #define PA4 4 #define PORTA5 5 #define PA5 5 #define PORTA6 6 #define PA6 6 #define PORTA7 7 #define PA7 7 /* Port B Input Pins Address */ #define PINB _SFR_IO8(0x03) /* PINB */ #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 /* Port B Data Direction Register */ #define DDRB _SFR_IO8(0x04) /* DDRB */ #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 /* Port B Data Register */ #define PORTB _SFR_IO8(0x05) /* PORTB */ #define PORTB0 0 #define PB0 0 #define PORTB1 1 #define PB1 1 #define PORTB2 2 #define PB2 2 #define PORTB3 3 #define PB3 3 #define PORTB4 4 #define PB4 4 #define PORTB5 5 #define PB5 5 #define PORTB6 6 #define PB6 6 #define PORTB7 7 #define PB7 7 /* Port C Input Pins Address */ #define PINC _SFR_IO8(0x06) /* PINC */ #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 /* Port C Data Direction Register */ #define DDRC _SFR_IO8(0x07) /* DDRC */ #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 /* Port C Data Register */ #define PORTC _SFR_IO8(0x08) /* PORTC */ #define PORTC0 0 #define PC0 0 #define PORTC1 1 #define PC1 1 #define PORTC2 2 #define PC2 2 #define PORTC3 3 #define PC3 3 #define PORTC4 4 #define PC4 4 #define PORTC5 5 #define PC5 5 #define PORTC6 6 #define PC6 6 #define PORTC7 7 #define PC7 7 /* Port D Input Pins Address */ #define PIND _SFR_IO8(0x09) /* PIND */ #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 /* Port D Data Direction Register */ #define DDRD _SFR_IO8(0x0A) /* DDRD */ #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 /* Port D Data Register */ #define PORTD _SFR_IO8(0x0B) /* PORTD */ #define PORTD0 0 #define PD0 0 #define PORTD1 1 #define PD1 1 #define PORTD2 2 #define PD2 2 #define PORTD3 3 #define PD3 3 #define PORTD4 4 #define PD4 4 #define PORTD5 5 #define PD5 5 #define PORTD6 6 #define PD6 6 #define PORTD7 7 #define PD7 7 /* Port E Input Pins Address */ #define PINE _SFR_IO8(0x0C) /* PINE */ #define PINE0 0 #define PINE1 1 #define PINE2 2 #define PINE3 3 #define PINE4 4 #define PINE5 5 #define PINE6 6 #define PINE7 7 /* Port E Data Direction Register */ #define DDRE _SFR_IO8(0x0D) /* DDRE */ #define DDE0 0 #define DDE1 1 #define DDE2 2 #define DDE3 3 #define DDE4 4 #define DDE5 5 #define DDE6 6 #define DDE7 7 /* Port E Data Register */ #define PORTE _SFR_IO8(0x0E) /* PORTE */ #define PORTE0 0 #define PE0 0 #define PORTE1 1 #define PE1 1 #define PORTE2 2 #define PE2 2 #define PORTE3 3 #define PE3 3 #define PORTE4 4 #define PE4 4 #define PORTE5 5 #define PE5 5 #define PORTE6 6 #define PE6 6 #define PORTE7 7 #define PE7 7 /* Port F Input Pins Address */ #define PINF _SFR_IO8(0x0F) /* PINF */ #define PINF0 0 #define PINF1 1 #define PINF2 2 #define PINF3 3 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 /* Port F Data Direction Register */ #define DDRF _SFR_IO8(0x10) /* DDRF */ #define DDF0 0 #define DDF1 1 #define DDF2 2 #define DDF3 3 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 /* Port F Data Register */ #define PORTF _SFR_IO8(0x11) /* PORTF */ #define PORTF0 0 #define PF0 0 #define PORTF1 1 #define PF1 1 #define PORTF2 2 #define PF2 2 #define PORTF3 3 #define PF3 3 #define PORTF4 4 #define PF4 4 #define PORTF5 5 #define PF5 5 #define PORTF6 6 #define PF6 6 #define PORTF7 7 #define PF7 7 /* Port G Input Pins Address */ #define PING _SFR_IO8(0x12) /* PING */ #define PING0 0 #define PING1 1 #define PING2 2 #define PING3 3 #define PING4 4 #define PING5 5 /* Port G Data Direction Register */ #define DDRG _SFR_IO8(0x13) /* DDRG */ #define DDG0 0 #define DDG1 1 #define DDG2 2 #define DDG3 3 #define DDG4 4 #define DDG5 5 /* Port G Data Register */ #define PORTG _SFR_IO8(0x14) /* PORTG */ #define PORTG0 0 #define PG0 0 #define PORTG1 1 #define PG1 1 #define PORTG2 2 #define PG2 2 #define PORTG3 3 #define PG3 3 #define PORTG4 4 #define PG4 4 #define PORTG5 5 #define PG5 5 /* Timer/Counter0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR0 { unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ unsigned int : 5; }; #define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) #endif /* __ASSEMBLER__ */ /* TIFR0 */ #define TOV0 0 #define OCF0A 1 #define OCF0B 2 /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR1 { unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ unsigned int : 2; }; #define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) #endif /* __ASSEMBLER__ */ /* TIFR1 */ #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 /* Timer/Counter Interrupt Flag Register */ #define TIFR2 _SFR_IO8(0x17) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR2 { unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ unsigned int : 5; }; #define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) #endif /* __ASSEMBLER__ */ /* TIFR2 */ #define TOV2 0 #define OCF2A 1 #define OCF2B 2 /* Timer/Counter3 Interrupt Flag Register */ #define TIFR3 _SFR_IO8(0x18) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR3 { unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ unsigned int : 2; }; #define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) #endif /* __ASSEMBLER__ */ /* TIFR3 */ #define TOV3 0 #define OCF3A 1 #define OCF3B 2 #define OCF3C 3 #define ICF3 5 /* Timer/Counter4 Interrupt Flag Register */ #define TIFR4 _SFR_IO8(0x19) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR4 { unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ unsigned int : 2; }; #define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) #endif /* __ASSEMBLER__ */ /* TIFR4 */ #define TOV4 0 #define OCF4A 1 #define OCF4B 2 #define OCF4C 3 #define ICF4 5 /* Timer/Counter5 Interrupt Flag Register */ #define TIFR5 _SFR_IO8(0x1A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR5 { unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ unsigned int : 2; }; #define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) #endif /* __ASSEMBLER__ */ /* TIFR5 */ #define TOV5 0 #define OCF5A 1 #define OCF5B 2 #define OCF5C 3 #define ICF5 5 /* Pin Change Interrupt Flag Register */ #define PCIFR _SFR_IO8(0x1B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PCIFR { unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ unsigned int : 5; }; #define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) #endif /* __ASSEMBLER__ */ /* PCIFR */ #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EIFR { unsigned int intf : 8; /* External Interrupt Flag */ }; #define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) #endif /* __ASSEMBLER__ */ /* EIFR */ #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EIMSK { unsigned int intm : 8; /* External Interrupt Request Enable */ }; #define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) #endif /* __ASSEMBLER__ */ /* EIMSK */ #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 /* General Purpose IO Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GPIOR0 { unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ }; #define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) #endif /* __ASSEMBLER__ */ /* GPIOR0 */ #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EECR { unsigned int eere : 1; /* EEPROM Read Enable */ unsigned int eepe : 1; /* EEPROM Programming Enable */ unsigned int eempe : 1; /* EEPROM Master Write Enable */ unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ unsigned int eepm : 2; /* EEPROM Programming Mode */ unsigned int : 2; }; #define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) #endif /* __ASSEMBLER__ */ /* EECR */ #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) /* EEDR */ #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 /* EEPROM Address Register Bytes */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GTCCR { unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ unsigned int : 5; unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ }; #define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) #endif /* __ASSEMBLER__ */ /* GTCCR */ #define PSRSYNC 0 #define PSR10 0 #define PSRASY 1 #define PSR2 1 #define TSM 7 /* Timer/Counter0 Control Register A */ #define TCCR0A _SFR_IO8(0x24) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR0A { unsigned int wgm0 : 2; /* Waveform Generation Mode */ unsigned int : 2; unsigned int com0b : 2; /* Compare Match Output B Mode */ unsigned int com0a : 2; /* Compare Match Output A Mode */ }; #define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) #endif /* __ASSEMBLER__ */ /* TCCR0A */ #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 /* Timer/Counter0 Control Register B */ #define TCCR0B _SFR_IO8(0x25) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR0B { unsigned int cs0 : 3; /* Clock Select */ unsigned int wgm02 : 1; /* */ unsigned int : 2; unsigned int foc0b : 1; /* Force Output Compare B */ unsigned int foc0a : 1; /* Force Output Compare A */ }; #define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) #endif /* __ASSEMBLER__ */ /* TCCR0B */ #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 /* Timer/Counter0 Register */ #define TCNT0 _SFR_IO8(0x26) /* TCNT0 */ #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 /* Timer/Counter0 Output Compare Register */ #define OCR0A _SFR_IO8(0x27) /* OCR0A */ #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 /* Timer/Counter0 Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) /* OCR0B */ #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 /* General Purpose IO Register 1 */ #define GPIOR1 _SFR_IO8(0x2A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GPIOR1 { unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ }; #define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) #endif /* __ASSEMBLER__ */ /* GPIOR1 */ #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x2B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GPIOR2 { unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ }; #define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) #endif /* __ASSEMBLER__ */ /* GPIOR2 */ #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SPCR { unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ unsigned int cpha : 1; /* Clock Phase */ unsigned int cpol : 1; /* Clock polarity */ unsigned int mstr : 1; /* Master/Slave Select */ unsigned int dord : 1; /* Data Order */ unsigned int spe : 1; /* SPI Enable */ unsigned int spie : 1; /* SPI Interrupt Enable */ }; #define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) #endif /* __ASSEMBLER__ */ /* SPCR */ #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SPSR { unsigned int spi2x : 1; /* Double SPI Speed Bit */ unsigned int : 5; unsigned int wcol : 1; /* Write Collision Flag */ unsigned int spif : 1; /* SPI Interrupt Flag */ }; #define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) #endif /* __ASSEMBLER__ */ /* SPSR */ #define SPI2X 0 #define WCOL 6 #define SPIF 7 /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* SPDR */ #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 /* Analog Comparator Control And Status Register */ #define ACSR _SFR_IO8(0x30) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ACSR { unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ unsigned int aco : 1; /* Analog Compare Output */ unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ unsigned int acd : 1; /* Analog Comparator Disable */ }; #define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) #endif /* __ASSEMBLER__ */ /* ACSR */ #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 /* On-Chip Debug Register */ #define OCDR _SFR_IO8(0x31) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_OCDR { unsigned int ocdr : 8; /* On-Chip Debug Register Data */ }; #define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) #endif /* __ASSEMBLER__ */ /* OCDR */ #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SMCR { unsigned int se : 1; /* Sleep Enable */ unsigned int sm : 3; /* Sleep Mode Select bits */ unsigned int : 4; }; #define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) #endif /* __ASSEMBLER__ */ /* SMCR */ #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_MCUSR { unsigned int porf : 1; /* Power-on Reset Flag */ unsigned int extrf : 1; /* External Reset Flag */ unsigned int borf : 1; /* Brown-out Reset Flag */ unsigned int wdrf : 1; /* Watchdog Reset Flag */ unsigned int jtrf : 1; /* JTAG Reset Flag */ unsigned int : 3; }; #define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) #endif /* __ASSEMBLER__ */ /* MCUSR */ #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_MCUCR { unsigned int ivce : 1; /* Interrupt Vector Change Enable */ unsigned int ivsel : 1; /* Interrupt Vector Select */ unsigned int : 2; unsigned int pud : 1; /* Pull-up Disable */ unsigned int : 2; unsigned int jtd : 1; /* JTAG Interface Disable */ }; #define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) #endif /* __ASSEMBLER__ */ /* MCUCR */ #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Store Program Memory Control Register */ #define SPMCSR _SFR_IO8(0x37) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SPMCSR { unsigned int spmen : 1; /* Store Program Memory Enable */ unsigned int pgers : 1; /* Page Erase */ unsigned int pgwrt : 1; /* Page Write */ unsigned int blbset : 1; /* Boot Lock Bit Set */ unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ unsigned int sigrd : 1; /* Signature Row Read */ unsigned int rwwsb : 1; /* Read While Write Section Busy */ unsigned int spmie : 1; /* SPM Interrupt Enable */ }; #define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) #endif /* __ASSEMBLER__ */ /* SPMCSR */ #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 /* Extended Z-pointer Register for ELPM/SPM */ #define RAMPZ _SFR_IO8(0x3B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_RAMPZ { unsigned int rampz : 2; /* Extended Z-Pointer Value */ unsigned int : 6; }; #define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) #endif /* __ASSEMBLER__ */ /* RAMPZ */ #define RAMPZ0 0 #define RAMPZ1 1 /* Stack Pointer */ #define SP _SFR_IO16(0x3D) #define SPL _SFR_IO8(0x3D) #define SPH _SFR_IO8(0x3E) /* Status Register */ #define SREG _SFR_IO8(0x3F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SREG { unsigned int c : 1; /* Carry Flag */ unsigned int z : 1; /* Zero Flag */ unsigned int n : 1; /* Negative Flag */ unsigned int v : 1; /* Two's Complement Overflow Flag */ unsigned int s : 1; /* Sign Bit */ unsigned int h : 1; /* Half Carry Flag */ unsigned int t : 1; /* Bit Copy Storage */ unsigned int i : 1; /* Global Interrupt Enable */ }; #define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) #endif /* __ASSEMBLER__ */ /* SREG */ #define SREG_C 0 #define SREG_Z 1 #define SREG_N 2 #define SREG_V 3 #define SREG_S 4 #define SREG_H 5 #define SREG_T 6 #define SREG_I 7 /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_WDTCSR { unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ unsigned int wde : 1; /* Watch Dog Enable */ unsigned int wdce : 1; /* Watchdog Change Enable */ unsigned int : 1; unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ }; #define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) #endif /* __ASSEMBLER__ */ /* WDTCSR */ #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 /* Clock Prescale Register */ #define CLKPR _SFR_MEM8(0x61) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_CLKPR { unsigned int clkps : 4; /* Clock Prescaler Select Bits */ unsigned int : 3; unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ }; #define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) #endif /* __ASSEMBLER__ */ /* CLKPR */ #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Power Reduction Register 2 */ #define PRR2 _SFR_MEM8(0x63) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PRR2 { unsigned int prram : 4; /* Power Reduction SRAM 3 */ unsigned int : 4; }; #define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) #endif /* __ASSEMBLER__ */ /* PRR2 */ #define PRRAM0 0 #define PRRAM1 1 #define PRRAM2 2 #define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1<