/* Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iomxxhva.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA. */ #ifndef _AVR_IOMXXHVA_H_ #define _AVR_IOMXXHVA_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iomxxhva.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0X00) #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0X03) #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC0 0 /* Reserved [0x7] */ #define PORTC _SFR_IO8(0x08) #define PC0 0 /* Reserved [0x9..0x14] */ #define TIFR0 _SFR_IO8(0x15) #define ICF0 3 #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8(0x16) #define ICF1 3 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define OSICSR _SFR_IO8(0x17) #define OSISEL0 4 #define OSIST 1 #define OSIEN 0 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF2 2 #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT2 2 #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0x20) #define EEAR _SFR_IO8(0x21) #define EEARL _SFR_IO8(0x21) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* Reserved [0x22] */ #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRSYNC 0 #define TCCR0A _SFR_IO8(0x24) #define TCW0 7 #define ICEN0 6 #define ICNC0 5 #define ICES0 4 #define ICS0 3 #define WGM00 0 #define TCCR0B _SFR_IO8(0x25) #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO16(0X26) #define TCNT0L _SFR_IO8(0X26) #define TCNT0H _SFR_IO8(0X27) #define OCR0A _SFR_IO8(0x28) #define OCR0B _SFR_IO8(0X29) #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8(0x2E) /* Reserved [0x2F..0x30] */ #define DWDR _SFR_IO8(0x31) #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8(0x34) #define OCDRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0x35) #define CKOE 5 #define PUD 4 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SIGRD 5 #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS1 1 #define CLKPS0 0 /* Reserved [0x62..0x63] */ #define PRR0 _SFR_MEM8(0x64) #define PRVRM 5 #define PRSPI 3 #define PRTIM1 2 #define PRTIM0 1 #define PRVADC 0 #define __AVR_HAVE_PRR0 ((1<